A through-substrate via is a vertical electrical connection passing completely through a substrate comprising integrated circuitry. Through-substrate vias may be used to create 3D packages in 3D integrated circuits and are an improvement over other techniques such as package-on-package because the density of through-substrate vias may be substantially higher. Through-substrate vias provide interconnection of vertically aligned electronic devices through internal wiring that significantly reduces complexity and overall dimensions of a multi-chip electronic circuit.
Common through-substrate via processes include formation of through-substrate via openings through at least some of the thickness of the substrate. A thin dielectric liner is then deposited to electrically insulate sidewalls of the through-substrate via openings. Adhesion and/or diffusion barrier material(s) may be deposited to line over the dielectric. The through-substrate via openings are then filled with conductive material. When the through-substrate via openings are formed only partially through the substrate (e.g., typical when processing bulk substrates), substrate material is removed from the opposite side of the substrate from which the via openings were formed to expose the conductive material within the via openings.
One highly desirable conductive through-substrate via material is elemental copper that is deposited by electrodeposition. Copper may be formed by initially depositing a seed layer within the through-substrate via openings followed by electrodepositing elemental copper from an electroplating solution. An example copper electroplating solution includes copper sulfate as a source of copper ions, sulfuric acid for controlling conductivity, and copper chloride for nucleation of suppressor molecules. It can be difficult to completely deposit a seed layer onto all of the sidewalls of a through-substrate via opening, particularly for high aspect ratio openings. If the sidewalls aren't completely covered, one or more voids can form which may render the substrate inoperable.
Many current through-substrate vias primarily composed of elemental copper-fill undergo thermal expansion at elevated temperature during subsequent thermal processing steps. Because of mismatched thermal expansion coefficients of copper and substrate silicon, the expanded copper via may lead to crack formation into the surrounding silicon substrate which may lead to inoperable circuitry.